1. Field of the Invention
The present invention relates to a nonvolatile memory device and, more particularly, to a nonvolatile memory cell array having common drain lines and a method of operating the same.
2. Description of the Related Art
Unlike a volatile memory device, a nonvolatile memory device maintains data even when power is not applied to the memory.
Generally, the nonvolatile memory device has a charge storage layer between a semiconductor substrate and a gate. Nonvolatile memory devices are largely classified into two types according to the structure of the charge storage layer: a floating gate type and an MNOS type.
The floating gate type of nonvolatile memory device has a structure including a tunnel dielectric layer, a floating gate, an inter-gate insulating layer, and a control gate, which are stacked on a semiconductor substrate. The floating gate where charge is stored is formed of a conductive layer.
The MNOS type of nonvolatile memory device has a metal nitride oxide semiconductor (MNOS) or a metal oxide nitride oxide semiconductor (MONOS) structure. That is, the nonvolatile memory device has a dielectric layer, acting as the charge storage layer, between the semiconductor substrate and the gate. The MNOS type of nonvolatile memory device stores data using a trap site in the dielectric layer and an interface thereof, for example, a trap site present in an interface between the dielectric layer and the semiconductor. In particular, in the case where the gate is formed of a polysilicon layer, the nonvolatile memory device has a silicon oxide nitride oxide semiconductor (SONOS) structure.
Referring to FIG. 1, according to prior art, a nonvolatile memory device may include a tunnel dielectric layer 11, a trap dielectric layer 12, a Is blocking dielectric layer 13, a gate G, and source and drain S and D formed on a semiconductor substrate 10 at both sides of the gate G, which are stacked over the semiconductor substrate 10. The nonvolatile memory device may further include spacers 14 and 15 formed on sidewalls of the gate G. The tunnel dielectric layer 11, the trap dielectric layer 12, and the blocking dielectric layer 13 are formed of an oxide layer, a nitride layer, and an oxide layer, respectively. The trap dielectric layer 12 acts as a charge storage layer.
The nonvolatile memory device is programmed by channel hot electron injection (CHEI). To induce the CHEI, a strong lateral electric field is created between the source S and the drain D, for example, by applying a voltage of 5V to the gate G and applying voltages of 0V and 5V to the source S and the drain D, respectively. As a result, hot electrons are created in a channel region in the vicinity of the source S. The hot electrons are injected into an interface between the tunnel dielectric layer 11 and the trap dielectric layer 12, or the trap dielectric layer 12 beyond energy barriers of the semiconductor substrate 10 and the tunnel dielectric layer 11. This electron injection increases the threshold voltage of the nonvolatile memory device. Accordingly, applying a voltage less than the increased threshold voltage to the gate G cannot enable a current to flow through the programmed device. It allows the stored data to be read.
The nonvolatile memory device is erased by hot hole injection (HHI). To induce the HHI, for example, when a voltage of −10V is applied to the gate G, a voltage of 5V is applied to the source S, and the drain D and the semiconductor substrate 10 is applied with a ground voltage or floated, hot holes created between the source S and the substrate are injected into an interface between the tunnel dielectric layer 11 and the trap dielectric layer 12, or the trap dielectric layer 12, resulting in the erasing.
Because the conventional nonvolatile memory device shown in FIG. 1 is programmed by a strong lateral electric field between the source S and the drain D, a distance between the source S and the drain D should be small, if possible. Accordingly, an overlapped width W between the drain D and the gate G must be secured above a certain level.
Also, there is a problem that threshold voltages of unselected cells are increased since disturbance occurs in the cells that share bit and source lines with the selected cells in programming the memory cell array having the common source line structure. That is, in the unselected cell that is applied with voltages of 0V and 5V to the source and the drain in the above-mentioned programming process not by sharing the word line with the selected cell but by sharing the bit and source lines, a lateral electric field is created by a potential difference between the source and the drain. As the voltage applied to the drain is increased for the purpose of increasing the potential difference between the source and the drain, a depletion layer of the drain is expanded and accordingly is closer to the source, such that the drain depletion layer and the source depletion layer are completely connected to each other. Because in this state, the drain electric field affects the source side to degrade diffusion potential in the vicinity of the source, a current will flow between the source and the drain without a formed channel. Accordingly, there is a problem that the threshold voltage of the unselected cell is increased, thereby programming an unintended cell.
One approach to programming and erasing data in a P-channel SONOS memory cell is disclosed in U.S. Pat. No. 6,720,614, entitled, “Operation Method for Programming and Erasing a Data in a P-channel SONOS Memory Cell,” issued to Hung-Sui Lin, et al.